Micro and nano electronics integrated circuit domain has been strongly driven by the advent of the Internet of Things (IoT). The constraints become very strong, especially in terms of power consumption and autonomy. Not only during the computing phases, but also during the standby or sleep phases. In such applications, the circuit’s behaviour will also have to meet new constraints mainly linked to changing energetic environment, automatic wake up on event (a real challenge for smart connected objects), data storage when the circuit is sporadically turned off, and ultra-low voltage power supply for instance. ON/OFF computing strategy and Dynamic Power Management are necessary in many applications with strong constraints, especially in terms of power consumption and autonomy. It is assumed that 75 billion objects, embedding several functions and/or various sensors and actuators, will be connected by 2025. The need to store and to access simultaneously an increasing amount of data requires energy-efficient embedded architectures, processes and design techniques. However, the continuously decreasing size of devices and increasing operating frequency leads to critical power consumption, which is a major challenge. Historical solutions to improve the energy efficiency in future applications are facing a wall (power gating, clock gating, voltage adaptation etc.). Therefore, there is an important need to propose new efficient solutions. On the other hand, since 2016 we entered in a novel era for MRAM memories, as its landscape has moved towards more industrial products & applications sold by key market players such as Everspin, Global Foundries, ARM, and Samsung for instance. However, integrating MRAM into more complex designs, like processors or microcontrollers, rises several scientific issues, related to the technology itself, but also to the benefits expected at the application level.
Such a technique is also called clock-less technique, meaning that in opposition to standard synchronous circuit there is no global clock computing in the whole circuit. This technique is based on a specific communication protocol, usually called handshake protocol. CEA-LIST has a strong experience for decades in such design techniques, which provide very low standby power consumption thus well adapted to IoT systems, enabling automatic sleep mode and instant wake up at gate level due to event based computation. It is delay insensitive by nature so insensitive to process variations, which is a significant aspect in very advanced processes. Thus, asynchronous design technique is obviously relevant for of normally-OFF systems. Regarding the design and use of an asynchronous MRAM memory, it is important to remember that memories, namely the bit cell arrays, natively behave within an asynchronous scheme. Timing constraints may then be added in the controller to fulfil synchronous design requirements. We thus choose to associate asynchronous MRAM and asynchronous processor to reduce the amount of design constraints. Moreover, the robustness provided by asynchronous design scheme naturally suits the variation of read/write requests durations in memories.
MRAM technology: the basic element of a Magnetic Random Access Memories is the Magnetic Tunnel Junction (MTJ). Such a device, which is non-volatile (NV) and considered as a resistive element, is composed of 2 ferromagnetic layers separated by an insulator. When both ferromagnetic layers have their magnetization oriented in the same direction the device resistance is low. On the other hand, when the magnetization of these layers are in opposite direction the device resistance is high. MTJ enables to easily code ‘0’ or ‘1’ logic data in a NV manner. In this project, we intend to use and evaluate the last 2 generations of MTJs: i) the peSTT-MRAM flavour, which is presently already commercialized thanks to its interesting set of features and particularly in terms of energy and ii) the SOT-MRAM which is the most emerging MRAM flavour that has obviously very good electrical properties in terms of endurance and writing speed, thus writing energy, and for which further technological improvement is expected in the next years.
We work on the 28nm FD-SOI process from STMicroelectronics, which offers really interesting features for energy efficiency. Indeed, its body biasing capabilities enable to speed up computational phases and to significantly reduce leakage power consumption during inactive phases. Moreover, this process is latchup resistant, which is an important feature for circuit’s robustness.
|Partner||Name||First name||Current position||Role & responsibilities in the project|
|SPINTEC||DI PENDINA||Gregory||IR-CNRS||Coordinator, WP1 leader Scientific and technical leader of WP2|
|SPINTEC||PRENAT||Guillaume||Engineer Researcher||Physics and device modeling|
|SPINTEC||FRAGOSO||Joao||Engineer Researcher||MRAM memories and synchronous proc. design|
|LIRMM||BENOIT||Pascal||Associate professor||Scientific and technical leader of WP4|
|LIRMM||NOVO||David||CR-CNRS||System level explorations|
|LIRMM||SORIANO||Theo||Ph. D.||MRAM hybridization strategies for NV proc.|
|CEA-LIST||CHRISTMANN||Jean-Frédéric||Engineer-Researcher||Scientific and technical leader of WP3 Asynchronous proc.design|
The project started on October 1st 2019 and will end-up on September 30 th 2023.